Avalanche diodes, which are sometimes loosely referred to as Zener diodes are commonly used for providing a reference voltages for analog circuits. One particular application is as part of an ESD protection clamp.
An important consideration in designing semiconductor circuits, however, is the need to avoid introducing special process steps that would increase the overall cost. Thus it is desirable to be able to include so-called free structures by making use of existing process steps. In a CMOS process, however, only limited variations can be made to available regions in order to form diodes. For instance, diodes can be created using n+/p-well, p+/n-well, p-well/n-well, and, to some extent, n+/p+ junctions by spacing the n+ and p+ regions far apart to avoid tunneling. In a 0.18 um process these combinations typically provide breakdown voltages of approximately 12V, 12V, 17V, and 4V, respectively. As a result avalanche diodes are available only with discrete breakdown voltage values.
In the case of power supply electrostatic discharge protection (ESD) clamps, breakdown voltages in the range of about 5V–10V are, however, required. Conventional diodes thus fail to provide the requisite breakdown voltages.
One proposed prior art solution is to make use of n+/p+ as the diode and make use of a blocked space such as a shallow trench isolation region (STI) 100 between the n+ region 102 and p+ region 104 as shown in FIG. 1. However, this is usually not possible, especially in the case of small dimension devices, due to inadequate tolerance in the mask alignment.
The present invention seeks to address the problem of providing suitable breakdown voltages for avalanche diodes without adding additional process steps to the CMOS process.